1. Field of the Invention
The present invention relates to a digital-to-analog converter and, more particularly, to a compact, low-power, digital to analog converter employing floating-gate technology.
2. Description of Related Art
It is often desirable to convert signals between the analog and digital domains. For example, most audio files are stored in digital form, such as MP3s and compact disks. These digital files must be converted to an analog signal in order to be heard through a speaker. This transformation is typically carried out using a digital to analog converter (“DAC”), which converts digital signals into analog signals.
Today, DACs are used in numerous applications. Often, it is desirable for the DACs to be small, fast, accurate, and consume a small amount of power. For example, it is generally desirable for MP3 players to be very small and to have a long battery life. In order to accomplish this, it is desirable to optimize each component to reduce its size and its power consumption.
Using conventional DACs, designers may not be able to provide a suitably small and efficient product without sacrificing quality and performance. Customers, however, desire superior products in small packages. Hence, in many DAC applications designers sacrifice speed and accuracy for size.
FIG. 1 is a schematic diagram illustrating a conventional DAC 100. As shown in FIG. 1, a DAC 100 may include an operational amplifier (“op-amp”) 110 connected to a ladder network 120 of capacitors (C1-Cn) 122a-d (collectively 122). Each capacitor 122 in the ladder network 120 is connected in parallel to each other capacitor 122 and is connected through a bit selection switch 130a-d (collectively 130) to a reference voltage (Vref) on one end and to the inverting input 114 of the op-amp 110 on the other end. The reference voltage is also connected to the non-inverting input 112 of the op-amp 110. The op-amp 110 in the DAC 100 is typically configured as in integrator with a feedback capacitor Cf 124 connected between the output 116 of the op-amp 110 and the inverting input 114.
In operation, each leg of the ladder network 120 represents one bit of data. The capacitors 122 may be selected so that the voltage measured at the output of the op-amp 110 is a predetermined value when only that capacitor is selected in the circuit 100. In order to achieve desired results, the capacitors 122 are typically selected such that each successive capacitor in the ladder has a capacitance double the one before it. Thus, in such an embodiment, C1 equals a predetermined base value and C2=2C1; C3=4C1; C4=8C1; and Cn2n−1Cn.
The increase in value of the capacitor 122 for each successive bit of resolution results in increasingly larger capacitor sizes. When embodied in CMOS technologies, the value of the capacitor 122 substantially corresponds to the size of the capacitor 122. Thus, using the embodiment above, C2 takes up approximately twice the surface area as C1. Furthermore, larger capacitors consume more power as it takes more power to charge the capacitor. Thus, since each bit of resolution requires an additional capacitor leg in the ladder network 120, each successive bit of resolution significantly increases the space and power requirements of the DAC.
In certain embodiments, DACs have been implemented using resistive networks, instead of capactive networks. Often, this is not a suitable solution in CMOS because such resistors typically have large footprints, consume a large amount of power, and tend to be inaccurate. In standard CMOS technology, resistors are implemented by utilizing passive devices such as polysilicon, diffusion, or well strips. These resistors typically consume large chip areas to realize high resistance values and further require laser trimming or other trimming techniques to achieve precise values.
Accordingly, there is a need in the art for a DAC that is smaller than conventional DACs.
Additionally, there is a need in the art for a DAC that consumes less power than conventional DACs.
Additionally, there is a need in the art for a DAC that provides high resolution without requiring great surface area on a silicon substrate.
Additionally, there is a need in the art for a DAC that has a fixed surface area requirement for each leg of the ladder network.
Additionally, there is a need in the art for resistors to be implemented in a smaller footprint.
Additionally, there is a need in the art for tunable CMOS resistors that are easy to manufacture and provide high accuracy.